Step 4 : (State T 4) In T 4, microprocessor decodes the opcode, and on the basis of the instruction received, it decides whether to enter state T 5 or to enter state T 1 of the next Machine Cycle of 8085 Microprocessor. Step 3 : (State T 3) During T 3, 8085 loads the data from the data bus in its Instruction Register and raises RD to high which disables the memory device. The memory device then places the contents of addressed memory location on the data bus (AD 0 – AD 7). In T 2, 8085 sends RD signal low to enable the addressed memory location. (However A 0 – A 7 remain available as they were latched during T 1). Step 2 : (State T 2) In T 2, low-order address disappears from the AD 0 – AD 7 lines. In opcode fetch machine cycle status signals are : IO/M = 0, S 1 = 1, S 0 = 1. IO/M specifies whether it is a memory or I/O operation, S 1 status specifies whether it is read/write operation S 1 and S 0 together indicates read, write, opcode fetch, machine cycle operation, or whether it is in HALT state. In T 1, 8085 also sends status signals IO/M, S 1, and S 0. Thus microprocessor activates ALE (Address Latch Enable) which is used to latch the low-order byte of the address in external latch before it disappears. The low-order byte of the PC is placed on the AD 0 – AD 7 lines which stays on only during T 1. The high-order byte of the PC is placed on the A 8 – A 15 lines. Step 1 : (State T 1): In T 1 state, the 8085 places the contents of program counter on the address bus. The following section describes the opcode fetch cycle in step by step manner. It varies from 4T states to 6T states as per the instruction. 1.15 (b) shows the timing diagram for Opcode Fetch Machine Cycle 8085. 1.15 (a) shows flow of data (opcode) from memory to the microprocessor and Fig. In this Machine Cycle in 8085, processor places the contents of the Program Counter on the address lines, and through the read process, reads the opcode of the instruction. Summary − So this instruction INR M requires 1-Byte, 3-Machine Cycles (Opcode Fetch, Memory Read, Memory Write) and 10 T-States for execution as shown in the timing diagram.The first Machine Cycle of 8085 Microprocessor of every instruction is opcode fetch cycle in which the 8085 finds the nature of the instruction to be executed. Here is the timing diagram of the execution of the instruction INR M 4050H memory locations content will be increased by 1 as HL register pair is having 16-bit address 4050H The tracing table of this instruction is as follows So after execution of the instruction INR M, the current content of location 4050H will become 06H. Let us consider that HL register pair is holding the 16-bit value 4050H as 16-bit address. Let us consider INR M as a sample instruction of this category. As R can have any of the eight values as mentioned, so there are eight opcodes possible for this type of instruction. In different assembly language core, this instruction is used for looping or as a count. All flags, except Cy flag, are affected depending on the result thus produced. The result of increment will be stored in R updating its previous content. So the previous value in R will get increased by amount 1 only. This instruction is used to add 1 with the contents of R. In 8085 Instruction set, INR is a mnemonic that stands for ‘INcRement’ and ‘R’ stands for any of the following registers or memory location M pointed by HL pair.
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